This invention relates to processor modules, and particularly to an integrated programmable external interrupt system for a central processing unit on a module.
Various conditions in a processor module require interrupting the normal flow of instructions executed by the central processing unit (CPU). Some of these conditions arise internal to the CPU (internal interrupts) and some arise external to the CPU (external interrupts). The present invention is directed to the handling of external interrupts.
Processor modules often contain plural application specific integrated circuits (ASICs), each being a potential source of interrupts. Prior processor modules relied on using one interrupt from each of the ASICs. This required the CPU to read ASIC interrupt registers to determine which interrupt(s) were active each ASIC. Potential interrupts in one ASIC do not necessarily have a higher priority than interrupts another ASIC. Moreover several ASICs can have active interrupts at the same time. Consequently, it was a complicated and time consuming task for the CPU to sort through the various interrupt registers to determine the highest priority interrupt.
Prior processor modules had no mechanism for changing the priorities of individual interrupts, once the module design was completed. Consequently, it was difficult or impossible to correct system problems which arose due to incorrect assignment of priorities.